Gate Fidelity & Error Rates

Track: Quantum Hardware & Providers · Difficulty: Beginner–Intermediate · Est: 14 min

Gate Fidelity & Error Rates

Overview

This page answers the question: “How close are real operations to the ideal gates in my circuit diagram?”

Gate fidelity and error rates are how hardware teams summarize operation quality. They’re central to performance because circuits apply many operations, and small imperfections accumulate.

Intuition

A single imperfect step might not matter much. But a long sequence of slightly imperfect steps can drift far from what you intended.

This connects directly to Noise & Errors:

every gate is a chance for the state to be nudged off-course
the longer the circuit (including routing overhead), the more chances for errors to compound

A helpful way to think about it:

Fidelity is like “how often does the operation behave as intended?”
Error rate is the complement: “how often does something go wrong?”

Even when two devices both report “high fidelity,” the difference between “very high” and “extremely high” can matter a lot once you apply many gates.

What This Metric Captures

Gate fidelity/error rate reporting usually captures:

Average quality of a gate type (single-qubit, two-qubit, sometimes measurement), measured with standardized calibration experiments.
How reliably a device can implement its native operations under typical conditions.
Trends over time if reported repeatedly (stability is a signal, even without exact numbers).

It also indirectly reflects the health of the control stack: calibration, pulse shaping, drift management, and noise environment.

What This Metric Misses

These metrics are often summaries, and summaries can hide what matters for workloads:

Average vs worst-case: an average can look good while a subset of qubits/links performs much worse.
Context dependence: performance can vary with scheduling, simultaneous operations, and calibration state.
Correlated errors: Noise & Errors emphasized that errors are not always independent; correlation can break simple reasoning.
Algorithm sensitivity: some circuits are more fragile than others even at the same nominal error rate.
End-to-end behavior: a gate metric doesn’t directly capture compilation, routing, measurement post-processing, or drift during a long job.

Most importantly, a fidelity number doesn’t tell you what circuit depth is “safe.” Depth depends on where errors occur, how they compound, and how much redundancy or mitigation is used.

Turtle Tip

When you read a gate fidelity claim, mentally multiply it by circuit length. Ask: “If I need many operations, does this quality hold across the qubits and links my circuit actually uses?”

Common Pitfalls

Treating one fidelity number as universal. Real performance varies by qubit, by link, and over time.
Assuming “average error” predicts “algorithm success.” Worst-case behavior and correlations can dominate.
Forgetting that routing increases gate count; topology and fidelity must be interpreted together.
Over-trusting a metric without asking how it was measured and whether it matches your usage pattern.

Quick Check

Why can small differences in error rate matter a lot for longer circuits?
What is one reason an average fidelity can be misleading?
How does connectivity indirectly affect the impact of gate errors?

So far we’ve discussed “capacity” (qubit count), “routing cost” (connectivity), and “operation quality” (fidelity). Next we’ll look at cost models and access patterns—because even a capable device can be impractical if it’s hard to access, slow to schedule, or expensive in time and workflow.

← Connectivity & Topology Cost Models & Access Patterns →