Circuit Depth & Width

Track: Quantum Gates & Circuits · Difficulty: Beginner · Est: 12 min

Circuit Depth & Width

Overview

To reason about quantum computation as a structure, we need simple performance-related concepts. Two of the most important are:

width: how many qubits a circuit uses,
depth: how many time steps of gates the circuit requires (after accounting for parallelism).

These ideas are essential because they connect the abstract circuit model to real constraints:

more qubits means a larger state space,
more depth means a longer coherent evolution before measurement.

We’ll keep this conceptual and avoid hardware specifics.

Intuition

Width

If a circuit has $n$ wires, it has width $n$ .

Width tells you how many qubits are “alive” in the computation.

More width means you can represent more joint structure (including entanglement across many qubits).

Depth

Depth is about how many layers of gates you apply in sequence.

Some gates can be applied at the same time if they act on different qubits. That’s parallelism.

So the depth is the number of “parallel layers” needed.

Why depth matters (conceptually):

As depth grows, the computation relies on maintaining quantum coherence for longer.
More steps also mean more opportunities for small imperfections to accumulate.

You don’t need device details to understand the high-level tradeoff:

shallow circuits are generally easier to execute reliably than very deep circuits.

Formal Description

Width

A circuit’s width is the number of qubits it uses.

If width is $n$ , the state is a vector in a $2^n$ -dimensional space:

|\psi\rangle \in \mathbb{C}^{2^n}.

Depth

A circuit’s depth is the minimal number of time steps needed if you schedule gates so that:

gates acting on disjoint sets of qubits can run in the same step,
gates that share a qubit must run in different steps.

You can think of it as grouping gates into layers:

U_{\text{circuit}} = L_d L_{d-1}\cdots L_1,

where each layer $L_j$ is a product of gates that can be applied in parallel (because they touch different qubits).

Explanation of notation:

$d$ is the depth.
Each $L_j$ is a “parallel slice in time.”
Applying layers sequentially updates the state step-by-step.

Parallelism vs sequential execution

Parallelism reduces depth without changing the overall computation.
Some computations inherently require sequential steps because later gates depend on earlier state changes.

We are not proving limits here; we are just defining the structural metrics.

Worked Example

Consider a 3-qubit circuit with these operations:

Step A: apply H on qubit 0.
Step B: apply X on qubit 2.
Step C: apply CNOT from qubit 0 to qubit 1.

A diagram might look like:

q0: ──[H]──●──
           │
q1: ───────⊕──
q2: ──[X]─────

Now schedule by parallel layers:

Layer 1: H on q0 and X on q2 can run together (they touch different qubits).
Layer 2: CNOT uses q0 and q1, so it must be after Layer 1.

So:

width = 3 (three wires)
depth = 2 (two parallel layers)

Interpretation:

Even though there are 3 gates, the circuit depth is 2 because two gates can run in parallel.

Turtle Tip

To estimate depth quickly: group gates into “layers” where no wire is used twice in the same layer.

Common Pitfalls

Don’t confuse “number of gates” with depth. Many gates can be parallel, so depth can be much smaller than gate count.
Don’t think width is “how many qubits you measure.” Width is how many qubits exist in the computation, regardless of whether you measure all of them.

Quick Check

What is the width of a circuit with 5 wires?
If two gates act on different qubits, can they be in the same depth layer?

We’ve defined the circuit model and how to describe its structure. Next we close the module by discussing universal gate sets: small collections of gates that are enough to build (exactly or approximately) any circuit you might want.

← Circuit Diagrams & Notation Universal Gate Sets →